Wireless communication devices, such as mobile phone handsets, require a very high level of integration of hardware and firmware/software in order to achieve the necessary density of functionality, i.e. to realise the necessary functionality in a minimum device volume and at a minimum cost. An optimal wireless communication device design must also minimise power consumption in order to increase the battery call time and/or stand-by time.
Wireless communication devices also incorporate a number of distinct and operably coupled sub-systems, in order to provide the wide variety of functions and operations that a complex wireless communication device needs to perform. Such sub-systems comprise radio frequency power amplification functions, radio frequency integrated circuits (RFIC) comprising radio frequency generation, amplification, filtering logic, etc. as well as baseband integrated circuits (BBIC) comprising audio circuits, encoding/decoding, (de)modulation functions, processing logic, etc. and memory units.
Interfaces, which are often standardised to allow commonality and increased functionality between different chip-set manufacturers and different handset manufacturers, are defined for communicating between the respective sub-systems.
In the field of mobile phones, a consortium of mobile phone manufacturers has been formed to define various sub-system interfaces, particularly interfaces for variants of the second generation (2x.G), third generation (3G) and fourth generation (4G) of cellular phones comprising communication technologies such as multimode transceivers additionally employing different access technologies such as wideband code division multiple access (WCDMA). This consortium is known as ‘DigRF’ and details of the defined interfaces and functionality thereof, particularly in a multimode mobile phone scenario, can be found at www.digrf.com. One interface being defined by the DigRF consortium is the Dual-Mode 2.5G and 3G interface baseband (BB)-radio frequency (RF) interface standard (also known as the 3G DigRF standard), which encompasses a serial interface for Control, Receive (Rx) and Transmit (Tx) variants of cellular phones chipsets. The Dual-Mode 2.5G/3G BB-RF integrated circuit (IC) interface is implemented using low voltage differential voltage pairs for data transfers.
Within 3G DigRF, the transmit data is referred to as ‘TxData’ in the direction from the BBIC to the RFIC and the receive data is referred to as ‘RxData’ routed in the direction from the RFIC to the BBIC. The RFIC-BBIC interface supports the following data rates:                (i) TxData: Low speed at SysClk/4 and High speed at 312 Mbps, and        (ii) RxData: Low speed at SysClk/4 and SysClk, and High speed at 312 Mbps,Where: SysClk (i.e. the system clock) may operate at 19.2 MHz, 26 MHz or 38.4 MHz.        
Data transmission between the baseband (BB) line drive and coordinating communication data flow from the BBIC to the RFIC and an RF line receiver is asynchronous in nature. Consequently, the Line receiver in the respective IC does not have the knowledge about the correct clock phase to be used for extracting the data. Thus, a synchronization pattern is transmitted close to a start of a frame to facilitate synchronization, and cross-correlation algorithms are used to determine a best clock phase to be used for extraction of data. As a result, synchronization and cross-correlation activities are key functions of the interface.
The 3G DigRF Consortium has standardised two operational modes for searching for a synchronization pattern of a received data stream, and thereafter performing cross-correlation over 16 bits of the synchronisation pattern, to identify an optimum phase to be used to extract data:                (i) Hunt Mode; and        (ii) Sleep Mode (Hunt-Sleep).        
The Hunt mode, as illustrated in FIG. 1, functions as a default mode of operation where the receiver always searches (hunts) for a synchronisation pattern on every received frame 110 in the incoming data from a Line Driver. In Hunt Mode 105, the cross-correlation is performed over the 16 bits of the synchronisation pattern 100 in each received frame 110; that is 16 bits are required to match the standard specified correlation pattern of 16'hA84B. Further, it is noteworthy that a threshold level of 16 bits is therefore required for synchronization.
Following a reset operation, and thereafter an enable system clock (SysClkEn) signal being asserted, the Interface Receiver will always come up in Hunt Mode 105 (default mode). In Hunt Mode 105, all of the clock phases and Line Receiver associated digital logic (e.g correlators) are enabled and the Interface Receiver controller is arranged to always search (hunt) for the synchronisation pattern in the received data. The phase enable signals (either with ‘8’ phase or ‘4’ phase) sent to a clock control module (CCM) are always high. This allows all the phase clocks to be enabled.
Thus, the Hunt mode 105 is the safest mode of operation, as it ensures that all of the phase clocks are enabled all of the time, and the received frames 110 are located and synchronised to the Line Driver transmitting phase using the known correlation pattern. In Hunt Mode the interface is always checking for the synchronisation pattern 100, except for the duration of the header and payload sections of the frame (post synchronization to end of frame). In Hunt Mode 105 the cross-correlation can be performed over maximum number of ‘16’ bits of the synchronisation pattern 100. A threshold level is required for synchronization, which can be user defined, with again a maximum value of ‘16’.
However, the Hunt mode of operation 105 consumes a maximum amount of power, which is undesirable particularly in a context of a wireless communication device. Thus, a power saving mode, termed hunt-sleep mode, has been defined by the DigRF consortium.
Referring now to FIG. 2, a timing diagram 200 illustrates a first hunt mode of operation 105 followed by a second mode of operation 205, termed ‘Hunt Sleep Mode’. Hunt Sleep Mode is a mode of operation that is similar to ‘hunt mode’ 105, except that the Interface Receiver is arranged to sample a first bit 210 after the received frame 110, in order to determine whether Line Receiver communication (and all of the circuitry supporting such communication) is able to go into a sleep mode (low power mode). Hunt-Sleep mode of operation (which is optional in the standard) is meant for use when there are large gaps in transmission on the interface. In Hunt-sleep mode 205, all of the phase clocks are disabled 220, thereby effectively turning ‘off’ the digital circuitry. Thus, a determination of a ‘1’ after the end of a received frame indicates that the Line Receiver needs to go into a sleep mode, otherwise the unit remains in normal hunt mode 105.
In contrast, a determination of a ‘0’ after the end of a received frame 110 enables all phase clocks and remains in the default Hunt Mode. In sleep mode, the Interface Receiver controller then performs edge detection 215 to identify a ‘1’ to ‘0’ transition, thereby indicating an exiting of sleep mode. After edge detection 215 of the ‘1’ to ‘0’ transition, indicating an exit of ‘hunt-sleep mode’ 205, all phase clocks are enabled and the Interface Receiver controller hunts for a synchronisation pattern recognition 100 from all subsequent incoming data frames.
In high speed DigRF applications there are eight zeros, whereas in low/medium speed one zero exists between the exiting of a sleep mode and a possible start of the next valid frame. The eight zeros at high speed and the one zero at low/medium speed are more than adequate to turn ‘on’ all of the required phase clocks, thus ensuring all phases are present and valid to identify the first bit of the synchronisation pattern 100 of the next received frame 100.
Again, in Hunt-Sleep Mode 205, correlation may be performed over a maximum of 16 bits of the synchronisation pattern 100. A threshold level is required for synchronization, which again may be user defined, with a maximum value of ‘16’. The correlation threshold may be programmed to a value less than ‘16’, but this will unilaterally increase the likelihood of false synchronisation detection.
An amount of power that may be saved using Hunt-Sleep mode depends upon the type of data frames being transferred across the interface, e.g. whether the data frames are transferred in a bursty manner or in a data stream manner. Thus, Hunt-Sleep mode is a mode to be used when the transfer of data frames (from a Line Driver to a Line Receiver) is known to be quiet for a specific length of time (for example greater than multiple frame lengths).
The Hunt-Sleep mode of operation 205 is a subset of the Hunt Mode of operation 105. In Hunt Sleep Mode of operation 205, the Line Driver determines when the Line Receiver transitions into Sleep mode. Once the Line Receiver detects it is going into sleep mode the Line Receiver disables the clock phases and turns off any digital logic associated with the Line Receiver.
A difference between Hunt Mode and Hunt-Sleep Mode is that Hunt-Sleep mode allows the Line Driver to control when the Line Receiver and receiver digital logic may be put to sleep. However, the Hunt-Sleep mode is still a power hungry mode, but it does allow the possibility of the Line Driver to control when it puts the Line Receiver to sleep.
Thus, a need therefore exists for a communication device incorporating integrated circuits/sub-systems and a corresponding data interface, and a method of saving power therefor, which is able to provide reduced power without incurring significant increased cost or complexity.